1. Technical Field
The present invention generally relates to the art of semiconductor devices and, particularly to a high efficient electro-static discharge (ESD) clamping device.
2. Description of the Related Art
ESD is a continuing problem in the design and manufacture of semiconductor devices. Integrated circuits (ICs) can be damaged by ESD events stemming from a variety of sources, in which large currents flow through the device. In one such ESD event, a packaged IC receives a charge when it is held by a human whose body is electro-statically charged. This type of event is known as a human body mode (HBM) ESD stress. For example, a charge of about 0.6 μC can be induced on a body capacitance of 150 pF, leading to electro-static potentials of 4 kV or greater. HBM ESD events can result in a discharge for about 100 nS with peak currents of several amperes to the IC. Another source of ESD is from metallic objects, known as the machine mode (MM) ESD source, which is characterized by a greater capacitance and lower internal resistance than the HBM ESD source. The MM ESD can result in ESD transients with significantly higher rise times than the HBM ESD source. A third ESD mode is the charged device model (CDM), which involves situations where an IC becomes charged and discharges to ground when the IC is inserted into a socket, and one or more of the pins of the IC package touch the grounded contacts of the socket. In this model, the ESD discharge current flows in the opposite direction in the IC than that of the HBM ESD source and the MM ESD source. CDM pulses also typically have very fast rise times compared to the HBM ESD source.
So far, many ESD clamping device (a kind of ESD protection devices) designs have been proposed for protecting ICs for ESD. One common technique for creating ESD clamping devices for protection of ICs is to create n-channel MOS (nMOS) devices, in each of which a parasitic bipolar transistor (e.g., a lateral NPN) associated with the nMOS device turns on to conduct ESD currents from the pad to ground. In order to enhance the ESD robustness of these clamping devices, some ESD implantations had been reported for inclusion into the manufacture process to modify device structures for ESD protection. Generally, an n-type ESD implantation is used to cover the lightly-doped drain (LDD) peak structure and make a deeper junction in nMOS devices for ESD protection. A p-type ESD implantation wholly underlying the drain region of the nMOS device is used to reduce a reverse junction breakdown voltage and allow earlier turn-on/activation of a parasitic lateral bipolar transistor in the NMOS device for ESD protection. In short, both of the n-type and p-type ESD implantations are selectively used in nMOS devices according to requirement of actual applications to yield a higher ESD robustness.
However, owning to the p-type ESD implantation, the reverse junction breakdown voltage of the nMOS device will be reduced to 6V˜7V. For a 5V application of normal operation, the reverse junction breakdown voltage is close to its operating voltage. Therefore, a leakage current of such nMOS device during a normal operation (i.e., in the situation of no ESD event occur) is excessively large, such leakage current cannot be tolerable when such nMOS device is applied for low leakage applications or products. Accordingly, how to minimize the large leakage current during the normal operation and/or keep the advantage of high turn-on efficiency is very important, so that the clamping devices could achieve higher efficiency for ESD protection.